Internet of Things (IoT) development has induced many low power applications of integrated circuits. Since an operation current of an integrated circuit in low power mode is quite small, capacitors with low capacitances are desired for high resolution applications utilizing switched capacitors and SAR (successive approximation register)-ADCs (analog-to-digital converters), for example.
A low capacitance capacitor, e.g. a sub-femtofarad (sub-fF) metal-oxide-metal (MOM) capacitor, in an integrated circuit often suffers from mismatch and is thus difficult to design. There are three conventional methods to form low capacitance capacitors: shrinking finger length, increasing the space between fingers, and connecting multiple capacitors in series.
However, shrinking finger length leads to worse mismatching performance and a mean shift of capacitors at the edge and the center of a capacitor array due to a smaller area of the capacitor fingers. Increasing space between fingers introduces a low metal density risk in process control of the integrated circuit. While a uniform metal density is usually desired according to a circuit design rule, a capacitor with a lower metal density compared to its surrounding components in the integrated circuit impacts the operation performance of the surrounding components. Lastly, connecting multiple conventional capacitors in series introduces an abutting problem, where the series connection needs an extra metal line and enlarges the area of the integrated circuit.
As such, existing capacitor structures are not entirely satisfactory for designing capacitors with low capacitances.